Physical timing closure
Physical timing closure is the process by which an FPGA or a VLSI design with a physical representation is modified to meet its timing requirements. Most of the modifications are handled by EDA tools based on directives given by a designer. The term is also sometimes used as a characteristic, which is ascribed to an EDA tool, when it provides most of the features required in this process.
Physical timing closure became more important with submicron technologies, as more and more steps of the design flow had to be made timing-aware. Previously only logic synthesis had to satisfy timing requirements.
With present deep submicron technologies it is unthinkable to perform any of the design steps of placement, clock-tree synthesis and routing without timing constraints. Logic synthesis with these technologies is becoming less important. It is still required, as it provides the initial netlist of gates for the placement step, but the timing requirements do not need to be strictly satisfied any more.
When a physical representation of the circuit is available, the modifications required to achieve timing closure are carried out by using more accurate estimations of the delays. Furthermore additional degrees of freedom for the modification of the design are available. At the designer’s disposal are not only a large set of directives with which EDA tools can be controlled to perform optimizations with different algorithms or parameters, but also scripting languages with which additional functions can be added.
Copyright (c) 2007 Alessandro Uber.
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