Content of this page has not been updated since 2011 and is kept like that only to serve as an historical reference, not representing the current career objectives of its owner.

Alessandro Uber
Professional services

I am offering professional design services as freelance consulting engineer in the field of VLSI design adopting standard-cell-based methodologies. Although experienced with the whole set of tasks required for the design closure of such integrated circuits, the designs, which will most benefit from my collaboration, are the ones requiring particular attention for issues related to physical timing closure.

I have experience and I am interested to support the following design flows:

  • Synopsys (logic synthesis) + Magma (physical implementation)
  • Synopsys (logic synthesis) + Cadence (physical implementation)
  • Synopsys (logic synthesis + physical implementation)
  • Magma (logic synthesis + physical implementation)
  • Cadence (logic synthesis + physical implementation)

In all such cases I am proficient in programming and in setting up work-arounds for EDA tools and design flows.

My professional position is often described with different denominations. I give here an expandable list of some of the most common ones:

  • ASIC Physical Design Engineer (see more...)
  • IC Physical Design Engineer (see more...)
  • SoC Design Engineer
  • VLSI Design Engineer
  • SoC Timing Closure Engineer

I am available to join a design team either at the customer's premises or by means of remote VPN connections. I am also available to perform design closure tasks at my premises in Munich, Germany either by myself or with small teams of freelance consultants, which I can assemble on demand.

I operate at all locations worldwide, compatibly with visa restrictions. 

Please contact me to receive detailed information about my background or to request a quotation.