I am a freelance engineer with a laurea degree in electronics of the University of Genoa in Italy.
I have been working as a freelance engineer between 2003 and 2011 offering consultancy for the design of digital integrated circuits, specialist at that time in the use of EDA tools to achieve design closure of the digital parts of VLSI designs. Although capable of performing all the tasks required to design these parts from concept to logical and physical verification, my expertise was more focused on the timing closure involving physical optimizations, hence the name of this website.
I currently hold a permanent position with a multinational semiconductor chip maker.
My proficiency in this field is the fruit of a professional path that starts with a thesis describing the design of an ASIC for the hardware implementation of a character recognition system. At that time (1995) in Italy the only available degree was the laurea degree, a kind of bachelor's and master's degree in one. This thesis work was the one required to complete my studies, which were primarily oriented to microelectronics.
Two very important steps in my career were the periods of employment with Accent (a joint venture between Cadence and ST Microelectronics) in Italy and with Magma Design Automation in Germany, with the former as design engineer and the latter as application engineer. While working for these two companies I was given the opportunity to do an in-depth study of EDA tools of two of the most important players in the EDA market, Cadence and Magma. I could then refine my ability to build further automation on top of existing EDA tools by means of scripting and programming of software interfaces, which is rather appreciated among customers and employers to address unpredictable design closure problems and to allow the integration of heterogeneous tools in the same design flow.
Copyright (c) 2007-2013 Alessandro Uber.